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rev. 1.3 aug. 2005 512mb, 1gb, 2gb regist ered dimms ddr2 sdram ddr2 registered sdram module 240pin registered module based on 512mb b-die 72-bit ecc * samsung electronics reserves the right to change products or specification without notice. information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granti ng any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about sams ung products, contact your nearest samsung office. 2. samsung products are not intended for use in life suppor t, critical care, medical, safety equipment, or similar applications where product failure coul dresult in loss of life or personal or physical harm, or any military or defense application, or any governm ental procurement to which specia l terms or provisions may apply. 4 .com u datasheet
rev. 1.3 aug. 2005 512mb, 1gb, 2gb regist ered dimms ddr2 sdram ddr2 registered dimm ordering information note: ?z? and ?y? of part number(11th digit) stand for lead-free products. note: ?3? of part number(12th digit) stand for dummy pad pcb products. part number density organization component composition number of rank height m393t6553bg(z)3-cd5/cc 512mb 64mx72 64mx8(k4t51083qb)*9ea 1 30mm m393t6553bg(z)0-cd5/cc 512mb 64mx72 64mx8(k4t51083qb)*9ea 1 30mm m393t2953bg(z)3-cd5/cc 1gb 128mx72 64mx8(k4t51083qb)*18ea 2 30mm m393t2953bg(z)0-cd5/cc 1gb 128mx72 64mx8(k4t51083qb)*18ea 2 30mm M393T2950BG(z)3-cd5/cc 1gb 128mx72 128mx4(k4t51043qb)*18ea 1 30mm M393T2950BG(z)0-cd5/cc 1gb 128mx72 128mx4(k4t51043qb)*18ea 1 30mm m393t5750bs(y)3-cd5/cc 2gb 256mx72 128mx4(k4t51043qb)*36ea 2 30mm m393t5750bs(y)0-cd5/cc 2gb 256mx72 128mx4(k4t51043qb)*36ea 2 30mm features ? performance range ? jedec standard 1.8v 0.1v power supply ? vddq = 1.8v 0.1v ? 200 mhz f ck for 400mb/sec/pin, 267mhz f ck for 533mb/sec/pin ? 4 banks ? posted cas ? programmable cas latency: 3, 4, 5 ? programmable additive latency: 0, 1 , 2 , 3 and 4 ? write latency(wl) = read latency(rl) -1 ? burst length: 4 , 8(in terleave/nibble sequential) ? programmable sequential / interleave burst mode ? bi-directional differential data-strobe (s ingle-ended data-strobe is an optional feature) ? off-chip driver(ocd) impedance adjustment ? on die termination ? average refresh period 7.8us at lower than t case 85 c, 3.9us at 85 c < t case < 95 c ? serial presence detect with eeprom ? ddr2 sdram package: 6 0ball fbga - 128mx4/64mx8 ? all of lead-free products are compliant for rohs note: for detailed ddr2 sdram operation, please refer to samsung?s device operation & timing diagram. d5(ddr2-533) cc(ddr2-400) unit speed@cl3 400 400 mbps speed@cl4 533 400 mbps speed@cl5 - -mbps cl-trcd-trp 4-4-4 3-3-3 ck address configuration organization row address column address bank address auto precharge 128mx4(512mb) based module a0-a13 a0-a9,a11 ba0-ba1 a10 64mx8(512mb) based module a0-a13 a0-a9 ba0-ba1 a10 4 .com u datasheet
rev. 1.3 aug. 2005 512mb, 1gb, 2gb regist ered dimms ddr2 sdram pin configurations (front side/back side) nc = no connect, rfu = reserved for future use 1. reset (pin 18) is connected to both oe of pll and reset of register. 2. the test pin (pin 102) is reserved for bus analysis probes and is not connected on normal memory modules (dimms) 3. nc/err_out ( pin 55) and nc/par_in (pin 68) are for optional function to check address and command parity. 4. cke1,s 1 pin is used for double side registered dimm. pin front pin back pin front pin back pin front pin back pin front pin back 1 v ref 121 v ss 31 dq19 151 v ss 61 a4 181 v ddq 91 v ss 211 dm5/dqs14 2 v ss 122 dq4 32 v ss 152 dq28 62 v ddq 182 a3 92 dqs 5 212 nc/dqs 14 3 dq0 123 dq5 33 dq24 153 dq29 63 a2 183 a1 93 dqs5 213 v ss 4 dq1 124 v ss 34 dq25 154 v ss 64 v dd 184 v dd 94 v ss 214 dq46 5 v ss 125 dm0/dqs9 35 v ss 155 dm3/dqs12 key 95 dq42 215 dq47 6dqs 0 126 nc/dqs 936 dqs 3 156 nc/dqs 12 65 v ss 185 ck0 96 dq43 216 v ss 7 dqs0 127 v ss 37 dqs3 157 v ss 66 v ss 186 ck 097 v ss 217 dq52 8 v ss 128 dq6 38 v ss 158 dq30 67 v dd 187 v dd 98 dq48 218 dq53 9 dq2 129 dq7 39 dq26 159 dq31 68 nc/par_in 188 a0 99 dq49 219 v ss 10 dq3 130 v ss 40 dq27 160 v ss 69 v dd 189 v dd 100 v ss 220 rfu 11 v ss 131 dq12 41 v ss 161 cb4 70 a10/ap 190 ba1 101 sa2 221 rfu 12 dq8 132 dq13 42 cb0 162 cb5 71 ba0 191 v ddq 102 nc(test) 222 v ss 13 dq9 133 v ss 43 cb1 163 v ss 72 v ddq 192 ras 103 v ss 223 dm6/dqs15 14 v ss 134 dm1/dqs10 44 v ss 164 dm8/dqs17 73 we 193 s 0 104 dqs 6 224 nc/dqs 15 15 dqs 1 135 nc/dqs 10 45 dqs 8 165 nc/dqs 17 74 cas 194 v ddq 105 dqs6 225 v ss 16 dqs1 136 v ss 46 dqs8 166 v ss 75 v ddq 195 odt0 106 v ss 226 dq54 17 v ss 137 rfu 47 v ss 167 cb6 76 s 1 4 196 a13 107 dq50 227 dq55 18 reset 138 rfu 48 cb2 168 cb7 77 odt1 197 v dd 108 dq51 228 v ss 19 nc 139 v ss 49 cb3 169 v ss 78 v ddq 198 v ss 109 v ss 229 dq60 20 v ss 140 dq14 50 v ss 170 v ddq 79 v ss 199 dq36 110 dq56 230 dq61 21 dq10 141 dq15 51 v ddq 171 cke1 4 80 dq32 200 dq37 111 dq57 231 v ss 22 dq11 142 v ss 52 cke0 172 v dd 81 dq33 201 v ss 112 v ss 232 dm7/dqs16 23 v ss 143 dq20 53 v dd 173 nc 82 v ss 202 dm4/dqs13 113 dqs 7 233 nc/dqs 16 24 dq16 144 dq21 54 nc 174 nc 83 dqs 4 203 nc/dqs 13 114 dqs7 234 v ss 25 dq17 145 v ss 55 nc/err_out 175 v ddq 84 dqs4 204 v ss 115 v ss 235 dq62 26 v ss 146 dm2/dqs11 56 v ddq 176 a12 85 v ss 205 dq38 116 dq58 236 dq63 27 dqs 2 147 nc/dqs 11 57 a11 177 a9 86 dq34 206 dq39 117 dq59 237 v ss 28 dqs2 148 v ss 58 a7 178 v dd 87 dq35 207 v ss 118 v ss 238 vddspd 29 v ss 149 dq22 59 v dd 179 a8 88 v ss 208 dq44 119 sda 239 sa0 30 dq18 150 dq23 60 a5 180 a6 89 dq40 209 dq45 120 scl 240 sa1 90 dq41 210 v ss pin description *the vdd and vddq pins are tied to the single power-plane on pcb. pin name description pin name description ck0 clock inputs, positive line odt0~odt1 on die termination ck 0 clock inputs, negative line dq0~dq63 data input/output cke0, cke1 clock enables cb0~cb7 data check bits input/output ras row address strobe dqs0~dqs8 data strobes cas column address strobe dqs 0~dqs 8 data strobes, negative line we write enable dm(0~8),dqs(9~17) data masks / data strobes (read) s 0, s 1 chip selects dqs 9~dqs 17 data strobes (read), negative line a0~a9, a11~a13 address inputs rfu reserved for future use a10/ap address input/autoprecharge nc no connect ba0, ba1 ddr2 sdram bank address test memory bus test tool (not connect and not useable on dimms) scl serial presence detect (spd) clock input v dd core power sda spd data input/output v ddq i/o power sa0~sa2 spd address v ss ground par_in parity bit for the address and control bus v ref input/output reference err_out parity error found in the address and control bus v ddspd spd power reset register and pll control pin 4 .com u datasheet
rev. 1.3 aug. 2005 512mb, 1gb, 2gb regist ered dimms ddr2 sdram input/output functional description symbol type function ck0 input positive line of the differential pair of system clock inputs that drives input to the on-dimm pll. ck 0 input negative line of the differential pair of system clock inputs that drives the input to the on-dimm pll. cke0~cke1 input activates the sdram ck signal when high and deactivates the ck signal when low. by deactivating the clocks, cke low initiates the power down mode, or the self refresh mode. s 0~s 1 input enables the associated sdram command decoder when low and disables decoder when high. when decoder is dis- abled, new commands are ignored but previous operations continue. these input signals also disable all outputs (except cke and odt) of the register(s) on the dimm when both inputs are high. odt0~odt1 input i/o bus impedance control signals. r as , cas , we input when sampled at the positive rising edge of the clock, cas , ras , and we define the operation to be executed by the sdram. v ref supply reference voltage for sstl_18 inputs v ddq supply isolated power supply for the ddr sdram output buffers to provide improved noise immunity ba0~ba1 input selects which sdram bank of four is activated. a0~a9,a10/ap a11~a13 input during a bank activate command cycle, address defines the row address. during a read or write command cycle, address defines the column address. in addition to the column address, ap is used to invoke autoprecharge operation at the end of the burst read or write cycle. if ap is high, autoprecharge is selected and ba0, ba1 defines the bank to be precharged. if ap is low, autoprecharge is disabled. during a precharge command cycle, ap is used in conjunction with ba0, ba1 to control which bank(s) to precharge. if ap is high, all banks will be precharged regardless of the state of ba0 or ba1. if ap is low, ba0 and ba1 are used to define which bank to pre- charge. dq0~63, cb0~cb7 in/out data and check bit input/output pins dm0~dm8 input masks write data when high, issued concurrently with input data. both dm and dq have a write latency of one clock once the write command is registered into the sdram. v dd , v ss supply power and ground for the ddr sdram input buffers and core logic dqs0~dqs17 in/out positive line of the differential data strobe for input and output data. dqs 0~dqs 17 in/out negative line of the differential data strobe for input and output data. sa0~sa2 input these signals are tied at the system planar to either v ss or v ddspd to configure the serial spd eeprom address range. sda in/out this bidirectional pin is used to transfer data into or out of the spd eeprom. a resistor must be connected from the sda bus line to v ddspd to act as a pullup. scl input this signal is used to clock data into and out of the spd eeprom. a resistor may be connected from the scl bus time to v ddspd to act as a pullup. v ddspd supply serial eeprom positive power supply (wired to a separate power pin at the connector which supports from 1.7 volt to 3.6 volt operation). reset input the reset pin is connected to the rst pin on the register and to the oe pin on the pll. when low, all register outputs will be driven low and the pll clocks to the drams and register(s) will be set to low level (the pll will remain synchro- nized with the input clock ) par_in input parity bit for the address and control bus. ( ?1 ? : odd, ?0 ? : even) err_out input parity error found in the address and control bus test in/out used by memory bus analysis tools (unused on memory dimms) 4 .com u datasheet
rev. 1.3 aug. 2005 512mb, 1gb, 2gb regist ered dimms ddr2 sdram functional block diagram: 512mb, 64mx72 module (populated as 1 rank of x8 ddr2 sdrams) rs 0 dqs0 dqs 0 dm0/dqs9 nc/dqs 9 dm/ rdqs nu/ rdqs cs dqs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 dqs1 dqs 1 dm1/dqs10 nc/dqs 10 dm/ rdqs nu/ rdqs cs dqs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 dqs2 dqs 2 dm2/dqs11 nc/dqs 11 dm/ rdqs nu/ rdqs cs dqs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 dqs3 dqs 3 dm3/dqs12 nc/dqs 12 dm/ rdqs nu/ rdqs cs dqs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 dqs8 dqs 8 dm8/dqs17 nc/dqs 17 dm/ rdqs nu/ rdqs cs dqs dqs cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d8 dqs4 dqs 4 dm4/dqs13 nc/dqs 13 dm/ rdqs nu/ rdqs cs dqs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 dqs5 dqs 5 dm5/dqs14 nc/dqs 14 dm/ rdqs nu/ rdqs cs dqs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d5 dqs6 dqs 6 dm6/dqs15 nc/dqs 15 dm/ rdqs nu/ rdqs cs dqs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d6 dqs7 dqs 7 dm7/dqs16 nc/dqs 16 dm/ rdqs nu/ rdqs cs dqs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d7 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda v ss d0 - d8 v dd /v ddq d0 - d8 d0 - d8 vref v ddspd serial pd wp notes : 1. dq-to-i/o wiring may be changed within a byte. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. unless otherwise noted, resister values are 22 ohms 1:1 r e g i s t e r rst s0 * ba0-ba1 a0-a13 ras cas we cke0 odt0 reset pck7 pck 7 rs o-> cs : ddr2 sdrams d0-d8 rba0-rba1 -> ba0-ba1 : ddr2 sdrams d0-d8 ra0-ra13 -> a0-a13 : ddr2 sdrams d0-d8 rras -> ras : ddr2 sdrams d0-d8 rcas -> cas : ddr2 sdrams d0-d8 rwe -> we : ddr2 sdrams d0-d8 rcke0 -> cke : ddr2 sdrams d0-d8 rodt0 -> odt0 : ddr2 sdrams d0-d8 p l l oe ck 0 ck0 reset pck0-pck6, pck8, pck9 -> ck : ddr2 sdrams d0-d8 pck 0-pck 6, pck 8, pck 9 -> ck : ddr2 sdrams d0-d8 pck7 -> ck : register pck 7 -> ck : register * s 0 connects to dcs and vdd connects to csr on the register. m393t6553bg(z)3 / m393t6553bg(z)0 4 .com u datasheet
rev. 1.3 aug. 2005 512mb, 1gb, 2gb regist ered dimms ddr2 sdram rs 0 dqs0 dqs 0 dm0/dqs9 nc/dqs 9 dm/ rdqs nu/ rdqs cs dqs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 dqs1 dqs 1 dm1/dqs10 nc/dqs 10 dm/ rdqs nu/ rdqs cs dqs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 dqs2 dqs 2 dm2/dqs11 nc/dqs 11 dm/ rdqs nu/ rdqs cs dqs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 dqs3 dqs 3 dm3/dqs12 nc/dqs 12 dm/ rdqs nu/ rdqs cs dqs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 dqs8 dqs 8 dm8/dqs17 nc/dqs 17 dm/ rdqs nu/ rdqs cs dqs dqs cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d8 dqs4 dqs 4 dm4/dqs13 nc/dqs 13 dm/ rdqs nu/ rdqs cs dqs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 dqs5 dqs 5 dm5/dqs14 nc/dqs 14 dm/ rdqs nu/ rdqs cs dqs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d5 dqs6 dqs 6 dm6/dqs15 nc/dqs 15 dm/ rdqs nu/ rdqs cs dqs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d6 dqs7 dqs 7 dm7/dqs16 nc/dqs 16 dm/ rdqs nu/ rdqs cs dqs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d7 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d9 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d10 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d11 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d12 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d17 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d13 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d14 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d15 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d16 rs 1 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda v ss d0 - d17 v dd /v ddq d0 - d17 d0 - d17 vref v ddspd serial pd wp notes : 1. dq-to-i/o wiring may be changed per nibble. 2. unless otherwise noted, resister values are 22 ohms 3. rs0 and rs1 alternate between the back and front sides of the dimm 1:2 r e g i s t e r rst s1 * ba0-ba1 a0-a13 ras cas we cke0 cke1 reset ** pck7** pck 7** rs 1-> cs : ddr2 sdrams d9-d17 rba0-rba1 -> ba0-ba1 : ddr2 sdrams d0-d17 ra0-ra13 -> a0-a13 : ddr2 sdrams d0-d17 rras -> ras : ddr2 sdrams d0-d17 rcas -> cas : ddr2 sdrams d0-d17 rwe -> we : ddr2 sdrams d0-d17 rcke0 -> cke : ddr2 sdrams d0-d8 rcke1 -> cke : ddr2 sdrams d9-d17 p l l oe ck 0 ck0 reset pck0-pck6, pck8, pck9 -> ck : ddr2 sdrams d0-d17 pck 0-pck 6, pck 8, pck 9 -> ck : ddr2 sdrams d0-d17 pck7 -> ck : register pck 7 -> ck : register * s 0 connects to dcs and s 0 connects to csr on a register, s 1 connects to dcs and s 0 connects to csr on another register. odt0 odt1 rodt0 -> odt0 : ddr2 sdrams d0-d8 rodt1 -> odt1 : ddr2 sdrams d9-d17 s0 * rs o-> cs : ddr2 sdrams d0-d8 ** reset , pck7 and pck 7 connects to both registers. other signals connect to one of two registers. functional block diagram: 1gb, 128mx72 module (populated as 2 rank of x8 ddr2 sdrams) m393t2953bg(z)3 / m393t2953bg(z)0 4 .com u datasheet
rev. 1.3 aug. 2005 512mb, 1gb, 2gb regist ered dimms ddr2 sdram vss rs 0 dqs0 dqs 0 dm cs dqs dqs dq0 dq1 dq2 dq3 i/o 0 i/o 1 i/o 2 i/o 3 d0 dm0/dqs9 nc/dqs 9 dm cs dqs dqs dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 d9 dqs1 dqs 1 dm cs dqs dqs dq8 dq9 dq10 dq11 i/o 0 i/o 1 i/o 2 i/o 3 d1 dm1/dqs10 nc/dqs 10 dm cs dqs dqs dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 d10 dqs2 dqs 2 dm cs dqs dqs dq16 dq17 dq18 dq19 i/o 0 i/o 1 i/o 2 i/o 3 d2 dm2/dqs11 nc/dqs 11 dm cs dqs dqs dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 d11 dqs3 dqs 3 dm cs dqs dqs dq24 dq25 dq26 dq27 i/o 0 i/o 1 i/o 2 i/o 3 d3 dm3/dqs12 nc/dqs 12 dm cs dqs dqs dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 d12 dqs5 dqs 5 dm cs dqs dqs dq40 dq41 dq42 dq43 i/o 0 i/o 1 i/o 2 i/o 3 d5 dm5/dqs14 nc/dqs 14 dm cs dqs dqs dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 d14 dqs4 dqs 4 dm cs dqs dqs dq32 dq33 dq34 dq35 i/o 0 i/o 1 i/o 2 i/o 3 d4 dm4/dqs13 nc/dqs 13 dm cs dqs dqs dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 d13 dqs6 dqs 6 dm cs dqs dqs dq48 dq49 dq50 dq51 i/o 0 i/o 1 i/o 2 i/o 3 d6 dm6/dqs15 nc/dqs 15 dm cs dqs dqs dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 d15 dqs8 dqs 8 dm cs dqs dqs cb0 cb1 cb2 cb3 i/o 0 i/o 1 i/o 2 i/o 3 d8 dm8/dqs17 nc/dqs 17 dm cs dqs dqs cb4 cb5 cb6 cb7 i/o 0 i/o 1 i/o 2 i/o 3 d17 dqs7 dqs 7 dm cs dqs dqs dq56 dq57 dq58 dq59 i/o 0 i/o 1 i/o 2 i/o 3 d7 dm7dqs16 nc/dqs 16 dm cs dqs dqs dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 d16 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda v ss d0 - d17 v dd /v ddq d0 - d17 d0 - d17 vref v ddspd serial pd wp notes : 1. dq-to-i/o wiring may be changed per nibble. 2. unless otherwise noted, resister values are 22 ohms 1:2 r e g i s t e r rst s0 * ba0-ba1 a0-a13 ras cas we cke0 odt0 reset ** pck7** pck 7** rs o-> cs : ddr2 sdrams d0-d17 rba0-rba1 -> ba0-ba1 : ddr2 sdrams d0-d17 ra0-ra13 -> a0-a13 : ddr2 sdrams d0-d17 rras -> ras : ddr2 sdrams d0-d17 rcas -> cas : ddr2 sdrams d0-d17 rwe -> we : ddr2 sdrams d0-d17 rcke0 -> cke : ddr2 sdrams d0-d17 rodt0 -> odt0 : ddr2 sdrams d0-d17 p l l oe ck 0 ck0 reset pck0-pck6, pck8, pck9 -> ck : ddr2 sdrams d0-d8 pck 0-pck 6, pck 8, pck 9 -> ck : ddr2 sdrams d0-d8 pck7 -> ck : register pck 7 -> ck : register * s 0 connects to dcs of register1, csr of register2. csr of register 1 and dcs of register 2 connects to vdd ** reset , pck7 and pck 7 connects to both registers. other signals connect to one of two registers. functional block diagram: 1gb, 128mx72 module (populated as 1 rank of x4 ddr2 sdrams) M393T2950BG(z)3 / M393T2950BG(z)0 4 .com u datasheet
rev. 1.3 aug. 2005 512mb, 1gb, 2gb regist ered dimms ddr2 sdram functional block diagram: 2gb, 256mx72 module (populated as 2 rank of x4 ddr2 sdrams) a0 serial pd a1 a2 sa0 sa1 sa2 scl sda v ss d0 - d35 v dd /v ddq d0 - d35 d0 - d35 vref v ddspd serial pd wp p l l oe ck 0 ck0 reset pck0-pck6, pck8, pck9 -> ck : ddr2 sdrams d0-d35 pck 0-pck 6, pck 8, pck 9 -> ck : ddr2 sdrams d0-d35 pck7 -> ck : register pck 7 -> ck : register * s 0 connects to dcs and s 0 connects to csr on a register, s 1 connects to dcs and s 0 connects to csr on another register. ** reset , pck7 and pck 7 connects to both registers. other signals connect to one of two registers. 1:2 r e g i s t e r rst s1 * ba0-ba1 a0-a13 ras cas we cke0 cke1 reset ** pck7** pck 7** rs 1-> cs : ddr2 sdrams d18-d35 rba0-rba1 -> ba0-ba1 : ddr2 sdrams d0-d35 ra0-ra13 -> a0-a13 : ddr2 sdrams d0-d35 rras -> ras : ddr2 sdrams d0-d35 rcas -> cas : ddr2 sdrams d0-d35 rwe -> we : ddr2 sdrams d0-d35 rcke0 -> cke : ddr2 sdrams d0-d17 rcke1 -> cke : ddr2 sdrams d18-d35 odt0 odt1 rodt0 -> odt0 : ddr2 sdrams d0-d17 rodt1 -> odt1 : ddr2 sdrams d18-d35 s0 * rs o-> cs : ddr2 sdrams d0-d17 vss rs 0 dqs0 dqs 0 dm cs dqs dqs dq0 dq1 dq2 dq3 i/o 0 i/o 1 i/o 2 i/o 3 d0 dm0/dqs9 nc/dqs 9 dm cs dqs dqs dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 d9 dqs1 dqs 1 dm cs dqs dqs dq8 dq9 dq10 dq11 i/o 0 i/o 1 i/o 2 i/o 3 d1 dm1/dqs10 nc/dqs 10 dm cs dqs dqs dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 d10 dqs2 dqs 2 dm cs dqs dqs dq16 dq17 dq18 dq19 i/o 0 i/o 1 i/o 2 i/o 3 d2 dm2/dqs11 nc/dqs 11 dm cs dqs dqs dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 d11 dqs3 dqs 3 dm cs dqs dqs dq24 dq25 dq26 dq27 i/o 0 i/o 1 i/o 2 i/o 3 d3 dm3/dqs12 nc/dqs 12 dm cs dqs dqs dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 d12 dqs5 dqs 5 dm cs dqs dqs dq40 dq41 dq42 dq43 i/o 0 i/o 1 i/o 2 i/o 3 d5 dm5/dqs14 nc/dqs 14 dm cs dqs dqs dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 d14 dqs4 dqs 4 dm cs dqs dqs dq32 dq33 dq34 dq35 i/o 0 i/o 1 i/o 2 i/o 3 d4 dm4/dqs13 nc/dqs 13 dm cs dqs dqs dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 d13 dqs6 dqs 6 dm cs dqs dqs dq48 dq49 dq50 dq51 i/o 0 i/o 1 i/o 2 i/o 3 d6 dm6/dqs15 nc/dqs 15 dm cs dqs dqs dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 d15 dqs8 dqs 8 dm cs dqs dqs cb0 cb1 cb2 cb3 i/o 0 i/o 1 i/o 2 i/o 3 d8 dm8/dqs17 nc/dqs 17 dm cs dqs dqs cb4 cb5 cb6 cb7 i/o 0 i/o 1 i/o 2 i/o 3 d17 dqs7 dqs 7 dm cs dqs dqs dq56 dq57 dq58 dq59 i/o 0 i/o 1 i/o 2 i/o 3 d7 dm7dqs16 nc/dqs 16 dm cs dqs dqs dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 d16 dm/ cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d18 dm/ cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d19 dm/ cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d20 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d21 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d23 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d22 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d24 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d26 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d25 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d27 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d28 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d29 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d30 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d32 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d31 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d33 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d35 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d34 rs 1 m393t5750bs(y)3 / m393t5750bs(y)0 4 .com u datasheet
rev. 1.3 aug. 2005 512mb, 1gb, 2gb regist ered dimms ddr2 sdram absolute maximum dc ratings note : 1. stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stre ss rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this s pecification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. storage temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, plea se refer to jesd51-2 standard. ac & dc operating conditions recommended dc operating conditions (sstl - 1.8) note : there is no specific device v dd supply voltage requirement for sstl-1.8 compliance. however under all conditions v ddq must be less than or equal to v dd . 1. the value of v ref may be selected by the user to provide optimum noise margin in the system. typically the value of v ref is expected to be about 0.5 x v ddq of the transmitting device and v ref is expected to track variations in v ddq . 2. peak to peak ac noise on v ref may not exceed +/-2% v ref (dc). 3. v tt of transmitting device must track v ref of receiving device. 4. ac parameters are measured with v dd , v ddq and v ddl tied together. symbol parameter rating units notes v dd voltage on v dd pin relative to v ss - 1.0 v ~ 2.3 v v 1 v ddq voltage on v ddq pin relative to v ss - 0.5 v ~ 2.3 v v 1 v ddl voltage on v ddl pin relative to v ss - 0.5 v ~ 2.3 v v 1 v in, v out voltage on any pin relative to v ss - 0.5 v ~ 2.3 v v 1 t stg storage temperature -55 to +100 c 1, 2 symbol parameter rating units notes min. typ. max. v dd supply voltage 1.7 1.8 1.9 v v ddl supply voltage for dll 1.7 1.8 1.9 v 4 v ddq supply voltage for output 1.7 1.8 1.9 v 4 v ref input reference voltage 0.49*v ddq 0.50*v ddq 0.51*v ddq mv 1,2 v tt termination voltage v ref -0.04 v ref v ref +0.04 v 3 4 .com u datasheet
rev. 1.3 aug. 2005 512mb, 1gb, 2gb regist ered dimms ddr2 sdram operating temperature condition note : 1. operating temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, pl ease refer to jesd51.2 standard. 2. at 0 - 85 c, operation temperature range are the temperature which all dram specification will be supported. 3. at 85 - 95 c operation temperature range, doubling refresh commands in frequency to a 32ms period ( trefi=3.9 us ) is required, and to ent er to self refresh mode at this temperature range, an emrs command is required to change internal refresh rate. input dc logic level input ac logic level ac input test conditions notes: 1. input waveform timing is referenced to the input signal crossing through the v ih/il (ac) level applied to the device under test. 2. the input signal minimum slew rate is to be maintained over the range from v ref to v ih (ac) min for rising edges and the range from v ref to v il (ac) max for falling edges as shown in the below figure. 3. ac timings are referenced with input waveforms switching from v il (ac) to v ih (ac) on the positive transitions and v ih (ac) to v il (ac) on the negative transitions. symbol parameter rating units notes toper operating temperature 0 to 95 c 1, 2, 3 symbol parameter min. max. units notes v ih (dc) dc input logic high v ref + 0.125 v ddq + 0.3 v v il (dc) dc input logic low - 0.3 v ref - 0.125 v symbol parameter min. max. units notes v ih (ac) ac input logic high v ref + 0.250 - v v il (ac) ac input logic low - v ref - 0.250 v symbol condition value units notes v ref input reference voltage 0.5 * v ddq v1 v swing(max) input signal maximum peak to peak swing 1.0 v 1 slew input signal minimum slew rate 1.0 v/ns 2, 3 v ddq v ih (ac) min v ih (dc) min v ref v il (dc) max v il (ac) max v ss < ac input test signal waveform > v swing(max) delta tr delta tf v ref - v il (ac) max delta tf falling slew = rising slew = v ih (ac) min - v ref delta tr 4 .com u datasheet
rev. 1.3 aug. 2005 512mb, 1gb, 2gb regist ered dimms ddr2 sdram idd specification pa rameters definition (idd values are for full operati ng range of voltage and temperature) symbol proposed conditions units notes idd0 operating one bank active-precharge current ; t ck = t ck(idd), t rc = t rc(idd), t ras = t rasmin(idd); cke is high, cs\ is high between valid commands; ad- dress bus inputs are switching; data bus inputs are switching ma idd1 operating one bank active-read-precharge current ; iout = 0ma; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t rc = t rc (idd), t ras = t rasmin(idd), t rcd = t rcd(idd); cke is high, cs\ is high between valid commands; address bus inputs are switching; data pattern is same as idd4w ma idd2p precharge power-down current ; all banks idle; t ck = t ck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating ma idd2q precharge quiet standby current ; all banks idle; t ck = t ck(idd); cke is high, cs\ is high; other control and address bus inputs are stable; data bus inputs are floating ma idd2n precharge standby current ; all banks idle; t ck = t ck(idd); cke is high, cs\ is high; other control and address bus inputs are switching; data bus inputs are switching ma idd3p active power-down current ; all banks open; t ck = t ck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mrs(12) = 0ma ma slow pdn exit mrs(12) = 1ma ma idd3n active standby current ; all banks open; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs\ is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching ma idd4w operating burst write current ; all banks open, continuous burst writes; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs\ is high between valid commands; address bus inputs are switching; data bus in- puts are switching ma idd4r operating burst read current ; all banks open, continuous burst reads, iout = 0ma; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t ras- max(idd), t rp = t rp(idd); cke is high, cs\ is high between valid commands; address bus inputs are switching; data pattern is same as idd4w ma idd5b burst auto refresh current ; t ck = t ck(idd); refresh command at every t rfc(idd) interval; cke is high, cs\ is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching ma idd6 self refresh current ; ck and ck\ at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating normal ma low power ma idd7 operating bank interleave read current ; all bank interleaving reads, iout = 0ma; bl = 4, cl = cl(idd), al = t rcd(idd)-1* t ck(idd); t ck = t ck(idd), t rc = t rc(idd), t rrd = t rrd(idd), t faw = t faw(idd), t rcd = 1* t ck(idd); cke is high, cs\ is high between valid com- mands; address bus inputs are stable during deselects; data pattern is same as idd4r; refer to the following page for detailed timing conditions ma 4 .com u datasheet
rev. 1.3 aug. 2005 512mb, 1gb, 2gb regist ered dimms ddr2 sdram operating current table(1-1) (t a =0 o c, vdd= 1.9v) m393t6553bg(z)3 / m393t6553bg(z)0 : 512mb(64mx8 *9) modul e * idd6 = dram current + standby current of pll and register. ** module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol d5 (ddr2-533@cl=4) cc (ddr2-400@cl=3) unit notes idd0 1,420 1,265 ma idd1 1,540 1,330 ma idd2p 562 522 ma idd2q 715 665 ma idd2n 730 670 ma idd3p-f 750 720 ma idd3p-s 375 365 ma idd3n 1,180 1,065 ma idd4w 2,340 1,725 ma idd4r 2,020 1,655 ma idd5b 2,275 2,125 ma idd6* normal 50 50 ma idd7 3,155 3,020 ma m393t2953bg(z)3 / m393t2953bg(z)0 : 1gb(64mx8 *18) module * idd6 = dram current + standby current of pll and register. ** module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol d5 (ddr2-533@cl=4) cc (ddr2-400@cl=3) unit notes idd0 1,790 1,665 ma idd1 1,920 1,770 ma idd2p 784 724 ma idd2q 1,110 1,040 ma idd2n 1,090 1,060 ma idd3p-f 1,190 1,130 ma idd3p-s 600 570 ma idd3n 1,480 1,415 ma idd4w 2,740 2,135 ma idd4r 2,420 2,055 ma idd5b 2,665 2,485 ma idd6* normal 99 99 ma idd7 3,785 3,785 ma 4 .com u datasheet
rev. 1.3 aug. 2005 512mb, 1gb, 2gb regist ered dimms ddr2 sdram operating current table(1-2) (t a =0 o c, vdd= 1.9v) M393T2950BG(z)3 / M393T2950BG(z)0 : 1gb(128mx4 *18) module * idd6 = dram current + standby current of pll and register. ** module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol d5 (ddr2-533@cl=4) cc (ddr2-400@cl=3) unit notes idd0 2,420 2,250 ma idd1 2,640 2,400 ma idd2p 784 724 ma idd2q 1,110 1,040 ma idd2n 1,090 1,060 ma idd3p-f 1,190 1,130 ma idd3p-s 600 570 ma idd3n 1,840 1,730 ma idd4w 3,820 2,900 ma idd4r 3,590 3,000 ma idd5b 4,150 3,880 ma idd6* normal 99 99 ma idd7 5,900 5,570 ma m393t5750bs(y)3 / m393t5750bs(y)0 : 2gb(128mx4 *36) module * idd6 = dram current + standby current of pll and register. ** module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol d5 (ddr2-533@cl=4) cc (ddr2-400@cl=3) unit notes idd0 3,250 3,010 ma idd1 3,520 3,220 ma idd2p 1,238 1,138 ma idd2q 1,880 1,770 ma idd2n 1,850 1,810 ma idd3p-f 2,050 1,950 ma idd3p-s 1,030 980 ma idd3n 2,620 2,500 ma idd4w 4,710 3,690 ma idd4r 4,330 3,700 ma idd5b 4,990 4,660 ma idd6* normal 198 198 ma idd7 7,140 6,600 ma 4 .com u datasheet
rev. 1.3 aug. 2005 512mb, 1gb, 2gb regist ered dimms ddr2 sdram input/output capacitance (v dd =1.8v, v ddq =1.8v, t a =25 o c) * dm is internally loaded to match dq and dqs identically. parameter symbol min max min max min max min max units part-number m393t6553bg(z)3 m393t6553bg(z)0 m393t2953bg(z)3 m393t2953bg(z)0 M393T2950BG(z)3 M393T2950BG(z)0 m393t5750bs(y)3 m393t5750bs(y)0 input capacitance, ck and ck cck - 11 - 11 - 11 - 11 pf input capacitance, cke and cs ci1 - 12 - 12 - 12 - 12 input capacitance, addr,ras ,cas ,we ci2 - 12 - 12 - 12 - 12 input/output capacitance, dq, dm, dqs, dqs cio - 10 - 10 - 10 - 10 4 .com u datasheet
rev. 1.3 aug. 2005 512mb, 1gb, 2gb regist ered dimms ddr2 sdram electrical characteristics & ac timing for ddr2-533/400 sdram (0 c < t case < 95 c; v ddq = 1.8v + 0.1v; v dd = 1.8v + 0.1v) refresh parameters by device density speed bins and cl, trcd, trp, trc and tras for corresponding bin timing parameters by speed grade (refer to notes for informations re lated to this table at the bottom) parameter symbol 256mb 512mb 1gb 2gb 4gb units refresh to active/refresh command time trfc 75 105 127.5 195 tbd ns average periodic refresh interval trefi 0 c t case 85 c 7.8 7.8 7.8 7.8 7.8 s 85 c < t case 95 c 3.9 3.9 3.9 3.9 3.9 s speed ddr2-533(d5) ddr2-400(cc) units bin (cl - trcd - trp) 4 - 4 - 4 3 - 3 - 3 parameter min max min max tck, cl=3 5 8 5 8 ns tck, cl=4 3.75 8 5 8 ns tck, cl=5 - - - - ns trcd 15 15 ns trp 15 15 ns trc 55 55 ns tras 40 70000 40 70000 ns parameter symbol ddr2-533 ddr2-400 units notes min max min max dq output access time from ck/ck tac -500 +500 -600 +600 ps dqs output access time from ck/ck tdqsck -450 +450 -500 +500 ps ck high-level width tch 0.45 0.55 0.45 0.55 tck ck low-level width tcl 0.45 0.55 0.45 0.55 tck ck half period thp min(tcl, tch) x min(tcl, tch) x ps clock cycle time, cl=x tck 3750 8000 5000 8000 ps dq and dm input hold time tdh 225 x275 x ps dq and dm input setup time tds 100 x150 x ps control & address input pulse width for each input tipw 0.6 x0.6 x tck dq and dm input pulse width for each input tdipw 0.35 x0.35 x tck data-out high-impedance time from ck/ck thz x tac max x tac max ps dqs low-impedance time from ck/ck tlz(dqs) tac min tac max tac min tac max ps dq low-impedance time from ck/ck tlz(dq) 2* tacmin tac max 2* tacmin tac max ps dqs-dq skew for dqs and associated dq signals tdqsq x 300 x 350 ps dq hold skew factor tqhs x 400 x 450 ps dq/dqs output hold time from dqs tqh thp - tqhs x thp - tqhs x ps write command to first dqs latching transition tdqss wl-0.25 wl+0.25 wl-0.25 wl+0.25 tck dqs input high pulse width tdqsh 0.35 x 0.35 x tck dqs input low pulse width tdqsl 0.35 x 0.35 x tck 4 .com u datasheet
rev. 1.3 aug. 2005 512mb, 1gb, 2gb regist ered dimms ddr2 sdram parameter symbol ddr2-533 ddr2-400 units notes min max min max dqs falling edge to ck setup time tdss 0.2 x 0.2 x tck dqs falling edge hold time from ck tdsh 0.2 x 0.2 x tck mode register set command cycle time tmrd 2 x 2 x tck write postamble twpst 0.4 0.6 0.4 0.6 tck write preamble twpre 0.35 x 0.35 x tck address and control input hold time tih 375 x 475 x ps address and control input setup time tis 250 x 350 x ps read preamble trpre 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 tck active to active command period for 1kb page size products trrd 7.5 x 7.5 x ns active to active command period for 2kb page size products trrd 10 x 10 x ns four activate window for 1kb page size products tfaw 37.5 37.5 ns four activate window for 2kb page size products tfaw 50 50 ns cas to cas command delay tccd 2 2 tck write recovery time twr 15 x 15 x ns auto precharge write recovery + precharge time tdal twr+trp x twr+trp x tck internal write to read command delay twtr 7.5 x10 x ns internal read to precharge command delay trtp 7.5 7.5 ns exit self refresh to a non-read command txsnr trfc + 10 trfc + 10 ns exit self refresh to a read command txsrd 200 200 tck exit precharge power down to any non-read command txp 2 x 2 x tck exit active power down to read command txard 2 x 2 x tck exit active power down to read command (slow exit, lower power) txards 6 - al 6 - al tck cke minimum pulse width (high and low pulse width) tcke 33 tck odt turn-on delay taond 2 2 2 2 tck odt turn-on taon tac(min) tac(max)+1 tac(min) tac(max)+1 ns odt turn-on(power-down mode) taonpd tac(min)+2 2tck+tac(m ax)+1 tac(min)+2 2tck+tac (max)+1 ns odt turn-off delay taofd 2.5 2.5 2.5 2.5 tck odt turn-off taof tac(min) tac(max)+ 0.6 tac(min) tac(max)+ 0.6 ns odt turn-off (power-down mode) taofpd tac(min)+2 2.5tck+ tac(max)+1 tac(min)+2 2.5tck+ tac(max)+1 ns odt to power down entry latency tanpd 3 3 tck odt power down exit latency taxpd 8 8 tck ocd drive mode output delay toit 0 12 0 12 ns minimum time clocks remains on after cke asynchronously drops low tdelay tis+tck +tih tis+tck +tih ns 4 .com u datasheet
rev. 1.3 aug. 2005 512mb, 1gb, 2gb regist ered dimms ddr2 sdram physical dimensions: 64mbx8 based 64mx72 module(1 rank) the used device is 64m x8 ddr2 sdram, fbga. ddr2 sdram part no : k4t51083qb register pll 1.27 0.10 2.70 1.0 max m393t6553bg(z)3 / m393t6553bg(z)0 units : millimeters a b 63.00 55.00 30.00 133.35 2.50 1.00 0.20 2.500.20 detail b 5.00 detail a 4.00 1.500.10 0.800.05 4.00 3.80 3.00 4.00 4 .com u datasheet
rev. 1.3 aug. 2005 512mb, 1gb, 2gb regist ered dimms ddr2 sdram physical dimensions: 64mbx8/128mbx4 based 1 28mx72 module(2/1 ranks) the used device is 64m x8 / 128m x4 ddr2 sdram, fbga. ddr2 sdram part no : k4t51083qb / k4t51043qb register pll 1.27 0.10 4.00 1.0 max register 1.7 max m393t 2953bg(z)3 / m393t2953bg(z)0 2.50 1.00 0.20 2.500.20 detail b 5.00 detail a 4.00 1.500.10 0.800.05 4.00 3.80 3.00 4.00 units : millimeters 133.35 30.00 a b 63.00 55.00 m393t 2950bg(z)3 / M393T2950BG(z)0 4 .com u datasheet
rev. 1.3 aug. 2005 512mb, 1gb, 2gb regist ered dimms ddr2 sdram physical dimensions: 128mbx4 based 256mx72 module(2 ranks) the used device is 128m x4 ddr2 sdram, fbga. ddr2 sdram part no : k4t51043qb m393t5750bs(y)3 / m393t5750bs(y)0 register pll 1.27 0.10 4.00 1.0 max 1.7 max 2.50 1.00 0.20 2.500.20 detail b 5.00 detail a 4.00 1.500.10 0.800.05 4.00 3.80 3.00 4.00 units : millimeters 133.35 30.00 a b 63.00 55.00 register register register 4 .com u datasheet
rev. 1.3 aug. 2005 512mb, 1gb, 2gb regist ered dimms ddr2 sdram ck0 ck 0 pll out1 outn reg.a reg.b feedback in feedback out in 0ns (nominal) c 120 ohms 120 ohms 120 ohms 120 ohms c note: 1. the clock delay from the input of the p ll clock to the input of any ddr2 sdram or register will be set to 0ns (nominal). 2. input, output, and feedback clock lines are terminated fr om line to line as shown, and not from line to ground. 3. only one pll output is shown per output type. any addi tional pll outputs will be wired in a similar manner. 4. termination resistors for the pll feedback path clocks are lo cated as close to the input pin of the pll as possible. ddr2 sdram ddr2 sdram 240 pin ddr2 registered dimm clock topology 4 .com u datasheet
rev. 1.3 aug. 2005 512mb, 1gb, 2gb regist ered dimms ddr2 sdram revision history revision 1.0 (jan. 2004) - initial release revision 1.1 (jun. 2004) - added lead-free part number in the ordering information - changed idd2p revision 1.2 (sep. 2004) - changed idd6 revision 1.3 (aug. 2004) - added dummy pad pcb product part nu mber in the ordering information 4 .com u datasheet

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